-- Group B Transmit Team
-- February 24, 2007
-- This file is a package file describing the port map to a framepointer

Library ieee;
Use ieee.std_logic_1164.all;

Package transmit_package Is
	Component framepointer
		Port(MoveInAddr					: In Std_logic_vector(9 downto 0);
			 Clock, Move, Set			: In Std_logic;
			 WriteInAddr				: In Std_logic_vector(9 downto 0);
			 OutputAddr					: Out Std_logic_vector(9 downto 0));
	End Component;
	
	Function bitAnd(b: Std_logic; v: Std_logic_vector(9 downto 0)) Return Std_logic_vector;
	
	Function move(v: Std_logic_vector(15 downto 0)) Return Std_logic_vector;
	
	Function forward(v: Std_logic_vector(16 downto 0)) Return std_logic_vector;
	
	Function backward(v: Std_logic_vector(16 downto 0)) Return std_logic_vector;

End transmit_package;

Package Body transmit_package Is
-- Function utilized in Generate statement
Function bitAnd(b: Std_logic; v: Std_logic_vector(9 downto 0)) Return Std_logic_vector Is
	Variable result: Std_logic_vector(9 downto 0);
Begin
	For i In 0 to 9 Loop
		result(i) := (b And v(i));
	End Loop;
	Return result;
End Function;
	
-- Function utilized for re-arranging pointer to front and back of buffer	
Function move(v: Std_logic_vector(15 downto 0)) Return std_logic_vector Is
	Variable result: Std_logic_vector(15 downto 0);
Begin
	result(0) := v(15);
	For i In 0 to 14 Loop
		result(i+1) := v(i);
	End Loop;
	Return result;
End Function;

Function forward(v: Std_logic_vector(16 downto 0)) Return std_logic_vector Is
	Variable result: Std_logic_vector(16 downto 0);
Begin
	result(16) := '0';
	For i In 0 to 15 Loop
		result(i) := v(i+1);
	End Loop;
	Return result;
End Function;

Function backward(v: Std_logic_vector(16 downto 0)) Return std_logic_vector Is
	Variable result: Std_logic_vector(16 downto 0);
Begin
	result(0) := '0';
	For i In 0 to 15 Loop
		result(i+1) := v(i);
	End Loop;
	Return result;
End Function;
End Package Body;